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AR# 22626

NC-Verilog - When I use an ISE 8.1i netgen-output netlist, the following error occurs: "*E,DUPUNI: Unit "worklib.glbl:v" multiply defined in files ".v" and ".v""

Description

General Description:

When I run ncverilog with the command line, as follows:

ncverilog -y $XILINX/verilog/src/simprims +libext+.v my_and_tb.v my_and2_translate.v my_and1_translate.v

two verilog netlist files are compiled, and I am receiving errors that glbl is defined twice:

ncvlog: *W,RECOME (my_and1_translate.v,78|10): recompiling module/udp worklib.glbl:v.

First compiled from line 78 of my_and2_translate.v.

ncvlog: *E,DUPUNI: Unit "worklib.glbl:v" multiply defined in files "my_and2_translate.v" and "my_and1_translate.v".

ncvlog: *E,MNPDEC: Module name (glbl) previously declared.

Why is this occurring?

Solution

NC-Verilog (single-step) is intended to closely replicate the behavior of Verilog-XL. Consequently, it gives an error if there is more than one definition of any modules. Since it compiles, elaborates, and simulates in one single invocation, it rather errors out and informs the user of the same.

You can work around this issue by using the 3-step process (an example is given below).

ncvlog -work worklib -cdslib cds.lib my_and_tb.v my_and2_translate.v my_and1_translate.v

ncelab -work worklib -cdslib cds.lib worklib.my_and_tb_v worklib.glbl

ncsim -cdslib cds.lib my_and_tb_v

Cadence is working on a switch for ncverilog to allow this to pass through (as this is valid, according to the verilog LRM).

AR# 22626
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article