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AR# 22629

8.1i Install - ISE Service Pack Release Notes (README)

Description


This README Answer Record contains the Release Notes for 8.1i Service Packs. The Release Notes include installation instructions and a list of the issues that are fixed.



NOTE: ISE Service Packs are cumulative; consequently, fixes found in Service Pack 1 are also found in Service Packs 2 and 3.



A successful installation of Xilinx ISE 8.1i Service Pack "x" updates your software version number to 8.1.0xi.



NOTES:

- The destination directory specified during the setup operation must contain an existing Xilinx ISE installation. Only existing files are updated. Any new device support not previously installed should first be installed from the Xilinx ISE CD before adding the Service Pack.

- You must set the XILINX environment variable before installing the Service Pack.



Installation Instructions for Windows Users

1. Download "8_1_0xi_win.exe" from:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp


2. Run "8_1_0xi_win.exe."



Installation Instructions for Red Hat Linux and Sun Solaris Users

1. Download "8_1_0xi_<platform>.zip from:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp


2. Move the zip file to an empty "staging" area, and unzip the downloaded file.



For example:

mv 8_1_0xi_<platform>.zip /home/<staging_dir>

cd /home/<staging_dir>

unzip 8_1_0xi_<platform>.zip



3. Run "setup."



NOTE: WebUpdate can also be used to download the Service Pack update on Linux and Windows platforms.

Solution


Issues Addressed in 8.1i Service Packs



CORE Generator



(SP1) - (Xilinx Answer 22558) - 8.1i CORE Generator - "ERROR:coreutil - sim:178 - Attempting to set invalid value: (Component_Name, 802).ERROR:coreutil..."

(SP1) - (Xilinx Answer 22571) - 8.1i ISE/CORE Generator - "ERROR (dpm_coregenDoCoreRegen): could not get required Target Language value"



Floorplanner



(SP3) - (Xilinx Answer 22733) - 8.1i Floorplanner/PACE - BRAM/MULT locations all show the same location value

(SP3) - (Xilinx Answer 23085) - 8.1i Floorplanner - Out of Memory or "could not allocate memory" error

(SP3) - (Xilinx Answer 23086) - 8.1i Floorplanner - DPRAM components cannot be dragged and dropped from one site to another



MAP



(SP2) - (Xilinx Answer 22314) - 7.1.04i MAP Virtex-4 - Extra registers in my DSP48 cause my design to fail in timing simulation and hardware when using the MAP -timing option



Project Navigator



(SP3) - (Xilinx Answer 23074) - 8.1i ISE - No IP cores appear in the New Source Wizard - IP selection window when creating a new Project Navigator project

(SP3) - (Xilinx Answer 23114) - 8.1i ISE - When I open a project in Project Navigator, a Missing Project Source Files dialog box reports: "The following project source files could not be found:"

(SP3) - (Xilinx Answer 23115) - 8.1i ISE - Pushing the Insert key on the keyboard displays the Add Existing Source dialog box

(SP3) - (Xilinx Answer 23116) - 8.1i ISE - When I click in an open area of the Language Templates window below the selectable templates, a fatal error occurs

(SP3) - (Xilinx Answer 22904) - 8.1.03i ISE - Project Navigator / Leonardo Spectrum integrated synthesis support will only be available through ISE 8.2i

(SP3) - (Xilinx Answer 23118) - 8.1i ISE - MAP process property; Map to Input function has inconsistent range of values for Spartan-3 netlist project

(SP3) - (Xilinx Answer 22858) - 8.1i ISE - Synthesis completes without errors, but Project Navigator reports "Process 'Synthesize' failed"

(SP2) - (Xilinx Answer 22838) - 8.1i ISE - A User Document source fails to appear in the Project Navigator "Source" view

(SP2) - (Xilinx Answer 22831) - 8.1i ISE - Migrating an ISE 7.1i project to ISE 8.1i gives: ERROR:ProjectMgmt - TOE: ITclInterp::ExecuteCmd gave Tcl result 'couldn't compile regular expression pattern: invalid escape \ sequence'.

(SP2) - (Xilinx Answer 22839) - 8.1i ISE - Project Navigator project file options are incorrectly available while a process is running

(SP2) - (Xilinx Answer 22840) - 8.1i ISE - Project Navigator takes several minutes to launch ChipScope Core Inserter on Linux

(SP1) - (Xilinx Answer 22207) - 8.1i ISE - When creating a new Verilog or VHDL source using the Project Navigator New Source Wizard, I find that there are only 12 cells available for Port Name entry

(SP1) - (Xilinx Answer 22554) - 8.1i ISE - The Project Navigator Project, Sources, and Process menu items are all disabled (grayed out)

(SP1) - (Xilinx Answer 22555) - 8.1i ISE - I am unable to drag-and-drop files from Windows Explorer into Project Navigator to open the files

(SP1) - (Xilinx Answer 22445) - 8.1i ISE - Project Navigator, Language Template "drag and drop" does not work

(SP1) - (Xilinx Answer 22556) - 8.1i ISE - Project Navigator is sending the wrong source file to implementation and simulation processes

(SP1) - (Xilinx Answer 22557) - 8.1i ISE - Project Navigator process, TDO to ABEL converter, under Design Utilities is missing

(SP1) - (Xilinx Answer 22559) - 8.1i ISE - When simulating an XPS design, the top-level system_stub.v(hd) source disappears from Sources window

(SP1) - (Xilinx Answer 22522) - 8.1i ISE - Project Navigator process, Copy Result to Working Project, for MPPR does not copy all files

(SP1) - (Xilinx Answer 22570) - 8.1i ISE - When I launch ModelSim with a custom ".do" file, the following message appears: "# invalid command name"

(SP1) - (Xilinx Answer 22444) - 8.1i ISE - Project Navigator process, Assign Package Pins, does not respond an EDIF or NGC project

(SP1) - (Xilinx Answer 22569) - 8.1i ISE - When I implement a top-level EDIF design, the following error occurs: "ERROR:NgdBuild:28 - Top-level input design file "top_cs.ngc" cannot be found or created"

(SP1) - (Xilinx Answer 22219) - 8.1i ISE - Project Navigator ABEL language flow issues

(SP1) - (Xilinx Answer 22443) - 8.1i ISE - A new HDL source created through the Project Navigator New Source Wizard does not get added to the Synthesis/Implementation view

(SP1) - (Xilinx Answer 22575) - 8.1i ISE - When I try to open a CDC file from Library View, Project Navigator reports "ERROR:ProjectMgmt - TOE: ITclInterp::ExecuteCmd gave Tcl result 'invalid command name "0"'

(SP1) - (Xilinx Answer 22436) - 8.1i ISE/EDK - When implementing an EDK design, error occurs: "ERROR: found identical ISE and XPS BMM files. Copying the BMM file from the XPS project is no longer needed. Please remove the BMM file from the ISE project"

(SP1) - (Xilinx Answer 22437) - 8.1i ISE/EDK - "ERROR:HDLCompilers:87 - "system_stub.v" line 185 Could not find module/primitive 'system'"

(SP1) - (Xilinx Answer 22439) - 8.1i ISE/EDK - Behavioral Simulation does not allow me to specify the configuration name in a simulation test bench

(SP1) - (Xilinx Answer 22572) - 8.1i ISE - Project Navigator does not show third-party synthesis support for automotive, rad-hard, and military devices

(SP1) - (Xilinx Answer 22574) - 8.1i ISE - Error occurs when running Simulate Behavioral Model: "ERROR:ProjectMgmt - TOE: ITclInterp::ExecuteCmd gave Tcl result 'can't execute "NotHere": no such file or directory'"

(SP1) - (Xilinx Answer 22573) - 8.1i ISE - "Generate PROM, ACE or JTAG File" process does not open iMPACT GUI if an IPF file is specified



Simulation



(SP3) - (Xilinx Answer 22961) - 8.1i COMPXLIB - The following error occurs when libraries are compiled on Windows: "ERROR:CAEInterfaces - child process Failed"

(SP3) - (Xilinx Answer 22473) - 7.1i NetGen - Incorrect simulation model generated for ODDR Tristate control primitive

(SP3) - (Xilinx Answer 23010) - 8.1i NetGen, Timing Simulation Virtex-4 - Simulation netlist for BRAM does not have EN_ECC_READ and EN_ECC_WRITE attributes

(SP3) - (Xilinx Answer 21593) - 7.1i NetGen, Timing Simulation Virtex-4 - The OSERDES component does not have a clock to out that matches the ODDR component

(SP3) - (Xilinx Answer 22820) - 8.1i Simulation, Virtex-4 - "Warning: Address DADDR=1001110 is invalid at X_DCM_ADV instance <instance_name> at time <time>"

(SP2) - (Xilinx Answer 22644) - 8.1i NetGen, Timing Simulation Virtex-4 - Verilog X_IDELAY model does not have a tap delay of 78ps when used in 'fixed' mode

(SP2) - (Xilinx Answer 22103) - 7.1 NetGen - If hierarchy is kept, a Global_logic0/Global_logic1 is generated without a driver in the timing simulation netlist

(SP2) - (Xilinx Answer 18115) - 8.1i/7.1i Simulation - DCM outputs are "0" and the DCM does not lock (UniSim and SimPrim VHDL models) (DCM reset requirement)

(SP1) - (Xilinx Answer 22473) - 7.1i NetGen - Incorrect simulation model generated for ODDR tristate control primitive

(SP1) - (Xilinx Answer 22432) - 8.1i SimPrim, Timing Simulation - When I load the SDF for an X_MULT18x18SIO, multiple errors occur: "Instance '/uut/mult_inst' does not have a generic named ''tpw_..." (VHDL, SDF)

(SP1) - (Xilinx Answer 22391) - 8.1i Simulation, Virtex-4 - Initialization of FIFO16 WRCOUNT and RDCOUNT in the simulation model does not match the hardware

(SP1) - (Xilinx Answer 22415) - 8.1i/7.1i Simulation, Virtex-4 - The UniSim BUFGCTRL VHDL model has 100 ps delay on output



Spartan-3



(SP2) - (Xilinx Answer 22368) - Spartan-3E - Special considerations for using the Input Delay Element

(SP2) - (Xilinx Answer 22513) - 8.1i Data2MEM, Spartan-3E - Memory initialized by Data2MEM after BitGen is incorrect

(SP2) - (Xilinx Answer 22747) - BitGen Spartan-3 - DRC error occurs when RSDS_25 and LVCMOS_25 are placed in the same bank



Timing/Speed Files



(SP3) - (Xilinx Answer 23087) - 8.1i Timing Analyzer/TRCE - Clock uncertainty being analyzed in hold time on global clock

(SP1) - (Xilinx Answer 12201) - Speeds Files - What speeds files are currently installed for Virtex/-E/-II/-II Pro/-4 and Spartan-II/-IIE/-3 device families in ISE?

(SP1) - (Xilinx Answer 20953) - Virtex-4 - Speeds File Revision History

(SP1) - (Xilinx Answer 21299) - Spartan-3E - Speeds File Revision History

(SP1) - (Xilinx Answer 22615) - 7.1i sp2 Timing Analyzer/trce/speeds file - Spartan-3E Period Checks are updated for DCM

(SP1) - (Xilinx Answer 18579) - 7.1i Timing Analyzer - Different setup time reported in setup/hold table for differential input

(SP1) - (Xilinx Answer 22613) - 8.1 SpeedPrint - Incorrect operating temperature range for -6Q speed grade is reported

(SP1) - (Xilinx Answer 22614) - 7.1.04i Timing Analyzer - Crashes when analyzing endpoints multiple times



WebUpdate



(SP1) - (Xilinx Answer 22541) - 8.1i WebUpdate - WebUpdate fails to display updates found on xilinx.com



XPower



(SP2) - (Xilinx Answer 22805) - 8.1i XPower - BLVDS power reported by Power Estimation Tool is incorrect

(SP1) - (Xilinx Answer 22604) - 8.1i XPower - Worst Case Mode removed from software



XST



(SP1) - (Xilinx Answer 22514) - 8.1i ISE - XST synthesis fails with "ERROR:Xst:3 - File not found : "

(SP1) - (Xilinx Answer 22515) - 8.1i ISE - XST synthesis fails with "ERROR:Xst:1585 - Cannot open file ' '. Please make sure that the file exists and that you have read permission for it"

(SP1) - (Xilinx Answer 22516) - 8.1i ISE - XST synthesis fails with "ERROR:HDLParsers:3221 - Can't read \ - Analysis of file <"file_name.prj"> failed"

(SP1) - (Xilinx Answer 22517) - 8.1i ISE - XST synthesis fails with "ERROR:Xst:1249 - Missing part name parameter (-p) - ERROR:Xst:425 - Undefined command: -ifmt"
AR# 22629
Date Created 09/04/2007
Last Updated 11/20/2010
Status Archive
Type General Article