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AR# 22632

ISE 8.1i, Spartan-3E - Known Issues affecting Spartan-3E device features in the 8.1i design tools

Description

Support for the Spartan-3E architecture officially begins with the ISE 8.1i design tools.

This Answer Record summarizes the 8.1i ISE design tools Known Issues related to Spartan-3E. Xilinx recommends that customers use the latest Xilinx design tools when targeting Spartan-3E devices.

You can access the latest service pack at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

Solution

Bitstream

When the device is in a master configuration mode, the generated CCLK will be different than the ConfigRate selected in the software. This problem has been fixed in ISE 8.1.01i. For more information, see (Xilinx Answer 22093).

Input Delay Element

The Spartan-3E device has a programmable input delay. Be aware of changes planned for ISE 8.1i Service Pack 1 and Service Pack 2 that will significantly affect the use of this feature. See (Xilinx Answer 22368) for more information on the design considerations that are strongly recommended until Service Pack 2 is available.

STARTUP_SPARTAN3E Schematic Symbol

The MBT pin on the STARTUP_SPARTAN3E component is erroneously removed during the MAP phase of implementation.

This problem has been fixed in the latest 8.1i Service Pack available at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 8.1i Service Pack 1.

For more information on this issue, see (Xilinx Answer 22633).

Limited Data2MEM Support

There is no Data2MEM support for XC3S1200E and XC3S1600E in ISE 8.1i. Support was added in 8.1 Service Pack 2. Data2MEM, however, works fine for XC3S100E, XC3S250E, and XC3S500E.

For more information on this issue, see (Xilinx Answer 22513).

BLVDS Outputs

BLVDS outputs do not work correctly. For more information on this issue, see (Xilinx Answer 22401).

This problem has been fixed in the latest 8.1i Service Pack available at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is 8.1i Service Pack 1.

Speed Files are Advance

The speed files that are installed with ISE 8.1i are at Advance status for XC3S250E, XC3S1200E, and XC3S1600E. These speed files should not be used for timing analysis. See (Xilinx Answer 22037) for the latest information pertaining to Spartan-3E speed files.

Timing Analyzer Support of Clocks from Dedicated Inputs

Timing Analyzer does not recognize clocks from dedicated inputs in the Clock and I/O timing dialog. The Clock and I/O timing dialog are accessed by selecting Analyze -> Against User Specified Paths -> By Defining Clock and I/O timing within Timing Analyzer. When analyzing normal user-defined constraints, Timing Analyzer correctly analyzes clocks from dedicated inputs. This issue will be fixed in a future design tools update. For more information on this issue, see (Xilinx Answer 21846).

For more information on Stepping specifications, see the Spartan-3E Data Sheet located at:

http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1211407&iLanguageID=1

For more information on how to receive Xilinx Customer Notice distribution e-mails or alerts, see (Xilinx Answer 18683).

AR# 22632
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article