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AR# 22666

LogiCORE Fibre Channel Arbitrated Loop v1.1 Core - Verilog timing simulation causes timing errors at the beginning of the simulation

Description

When I perform a Verilog timing simulation of the Fibre Channel Arbitrated Loop v1.1 core, the following timing errors appear at the beginning of the simulation: 

 

"# ** Error: C:/libs/I.25/mti61b/./simprims_ver/simprims_ver_source.v(23155): $period( posedge CLKA:202679 ps, :204045 ps, 2220 ps ); 

 # Time: 204045 ps Iteration: 1 Instance: /testbench/FC_INST_1/\fc_al_core/BU2/U0/fc1_inst/fc1_rx_inst/async_fifo_inst/fifo_ram_inst_0\ 

 # ** Error: C:/libs/I.25/mti61b/./simprims_ver/simprims_ver_source.v(23155): $period( posedge CLKA:202682 ps, :204048 ps, 2220 ps ); 

 # Time: 204048 ps Iteration: 1 Instance: /testbench/FC_INST_1/\fc_al_core/BU2/U0/fc1_inst/fc1_rx_inst/async_fifo_inst/preview_ram_inst\ 

 # ** Error: C:/libs/I.25/mti61b/./simprims_ver/simprims_ver_source.v(23155): $period( posedge CLKA:202700 ps, :204066 ps, 2220 ps ); 

 # Time: 204066 ps Iteration: 1 Instance: /testbench/FC_INST_1/\fc_al_core/BU2/U0/fc1_inst/fc1_rx_inst/async_fifo_inst/fifo_ram_inst_1\ 

 # ** Error: C:/libs/I.25/mti61b/./simprims_ver/simprims_ver_spartan3a_SMART_source.v(9669): $period( posedge RXUSRCLK2:202795 ps, :204161 ps, 2750 ps ); 

 # Time: 204161 ps Iteration: 2 Instance: /testbench/FC_INST_1/\mgt_gig/GT11_1XFC_2_INST\"

Solution

These timing errors are due to the GT11 putting out an impossbly high frequency on the RXRECCLK output shortly after power-up. The errors can be safely ignored.

AR# 22666
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article