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AR# 22671

PCI/PCI-X CORE Generator UCF Generator v1.0 - Not all UCF files meet timing


Files generated by the v1.0 CORE Generator Virtex-4 UCF Generator do not always meet timing. Is this a known issue?


It is known that not all UCFs generated by the UCF Generator will meet timing. Users must verify that the UCF file generated will meet timing on their given device, package, and speed grade combination.

Most problems are due to trying to implement in "large" devices. In larger devices, the IDELAY cannot compensate for the larger clock delay exhibited by larger die sizes.

Moving to higher speed grades may reduce the clock delay, improving the timing.

Following is a list of known failing UCF files at the time of the 8.1i IP_1I release. These results are based on 8.1i design tools.

PCI 33 MHz, Virtex4, global clocks, -10 speed


xc4vfx100*-10 will not meet timing

xc4vfx140*-10 will not meet timing

xc4vlx100*-10 will not meet timing

xc4vlx160*-10 will not meet timing

xc4vlx200*-10 will not meet timing

PCI 66 MHz, Virtex4, regional clocks, -11 speed


xc4vfx*-11 placements on the right side when viewed top-down will not meet timing.

This is the MGT column 0 side or also the PPC side of the device.

For other parts and packages, PCI 66 timing is either met or is close enough that it is feasible timing can be met by increasing the PAR effort level or by using Floorplanning to get a better placement.

PCIX 133 MHz, Virtex4, global clocks, -11 speed


xc4vfx140*-11 will not meet timing

xc4vlx200*-11 will not meet timing

It is likely other UCFs for parts and packages, not explicitly listed above, may fail depending on the exact location and device selected by the user. Please keep in mind the UCF Generator is provided to allow users to produce UCF files that they can verify work in their designs.

Xilinx recommends that you verify the correctness of the implementation resulting from the use of files generated by the UCF Generator before committing to its use as a basis for a board or system level design. At minimum, you must:

1. Verify timing closure by performing static timing analysis on a fully placed and routed design implemented with this UCF file.

2. Verify the pin location constraints in this UCF file are compliant with the simultaneously switching output (SSO) guidelines for the targeted FPGA device and package.

3. Verify the board level routability of the pin location constraints in this UCF file. Note that the PCI and PCI-X specifications cite specific trace length requirements for full compliance.

AR# 22671
Date 12/15/2012
Status Active
Type General Article