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AR# 22676

8.1 sp1 Virtex-II Pro - "INTERNAL_ERROR:Pack:pktbaplacepacker.c:409:1.73.8.4"

Description

Keywords: -timing , timing, driven, pack, pktbaplacepacker

A problem has been seen in 8.1i sp1 where the timing-driven packing algorithm incorrectly merged two flops with conflicting control signals into the same slice, leading to the following failure:

Running timing-driven packing...

Phase 15.24
Phase 15.24 (Checksum:8f0d171) REAL time: 1 mins 32 secs

INTERNAL_ERROR:Pack:pktbaplacepacker.c:409:1.73.8.4 - Unable to obey placement
request which requires the combination of the following comp blocks into the
SLICE_X64Y75 site. comp: PCI_CORE/PCI_LC/MASTER/$1I2914/ADDR_BE_Q comp:
PCI_CORE/PCI_LC/IFRAME_I- The fragment blocks involved are as follows: FLOP
symbol "PCI_CORE/PCI_LC/MASTER/$1I2914/$1I2862" (Output Signal =
PCI_CORE/PCI_LC/MASTER/$1I2914/ADDR_BE_Q) MUXF5 symbol
"PCI_CORE/PCI_LC/MASTER/FRAME/$1I3419" (Output Signal =
PCI_CORE/PCI_LC/NS_FRAME-) LUT symbol "PCI_CORE/PCI_LC/MASTER/FRAME/$1I3368"
(Output Signal = PCI_CORE/PCI_LC/MASTER/FRAME/NS_S_0) LUT symbol
"PCI_CORE/PCI_LC/MASTER/FRAME/$1I3470" (Output Signal =
PCI_CORE/PCI_LC/MASTER/FRAME/NS_S_1) FLOP symbol
"PCI_CORE/PCI_LC/MASTER/FRAME/IFRAME_I-" (Output Signal =
PCI_CORE/PCI_LC/IFRAME_I-) The clock enable signals don't agree.
INTERNAL_ERROR:Pack:pktbaplacepacker.c:409:1.73.8.4 - Unable to obey placement
request which requires the combination of the following comp blocks into the
SLICE_X67Y67 site. comp: M_CBE<7> comp: PCI_CORE/PCI_LC/IREQ64_I- The
fragment blocks involved are as follows: FLOP symbol
"PING64_INST/M_CBE_reg_7" (Output Signal = M_CBE<7>) MUXF5 symbol
"PCI_CORE/PCI_LC/MASTER/REQ64/$1I3568" (Output Signal =
PCI_CORE/PCI_LC/NS_REQ64-) LUT symbol "PCI_CORE/PCI_LC/MASTER/REQ64/$1I3569"
(Output Signal = PCI_CORE/PCI_LC/MASTER/REQ64/NS_S_0) LUT symbol
"PCI_CORE/PCI_LC/MASTER/REQ64/$1I3561" (Output Signal =
PCI_CORE/PCI_LC/MASTER/REQ64/NS_S_1) FLOP symbol
"PCI_CORE/PCI_LC/MASTER/REQ64/IREQ64_I-" (Output Signal =
PCI_CORE/PCI_LC/IREQ64_I-) The clock enable signals don't agree.

This problem is thought to be a regression introduced by sp1.

Solution

This problem is scheduled to be fixed in 8.1i sp2. Meanwhile, the problem can be avoided by turning off the timing-driven packing option or by using MAP packing constraints to prevent the incorrect packing behavior.
AR# 22676
Date Created 09/04/2007
Last Updated 11/16/2008
Status Archive
Type General Article