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AR# 22677

ML410 BSB - What is required to meet timing with a BSB-based ML410 design containing an OPB_PCI Core?

Description

What is required to meet timing with a BSB-based ML410 design containing an OPB_PCI Core?

Solution

Added the following to the UCF file for the ML410 with OPB_PCI in the design: 

 

1) Area Groups  

 

PLB2OPB 

AREA_GROUP "pblock_plb2opb" RANGE= SLICE_X34Y140:SLICE_X51Y191; 

INST "plb2opb" AREA_GROUP = "pblock_plb2opb"; 

INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CARRY_MUX*" AREA_GROUP = "pblock_plb2opb"; 

INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CYMUX_FIRST*" AREA_GROUP = "pblock_plb2opb"; 

INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/_n*" AREA_GROUP = "pblock_plb2opb"; 

INST "plb/plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/*" AREA_GROUP = "pblock_plb2opb"; 

 

OPB2PLB 

AREA_GROUP "opb2plb" RANGE=SLICE_X20Y104:SLICE_X33Y139, SLICE_X34Y96:SLICE_X51Y139; 

INST "opb2plb" AREA_GROUP = "opb2plb"; 

 

OPB_SPI 

AREA_GROUP "pblock_spi_eeprom" RANGE=SLICE_X54Y92:SLICE_X67Y111; 

INST "spi_eeprom" AREA_GROUP = "pblock_spi_eeprom"; 

 

 

2) PCI to OPB constraint (change "FROMTO" constraint from 10 ns to 9.9 ns and add the "datapathonly" keyword) 

 

Here is the exact UCF string user needs to copy and paste upon BSB design: 

 

TIMESPEC TS_PCI_BUS = FROM PCI_CLK TO SYS_CLK 9900 ps datapathonly; 

 

Notice that BSB delivers constraint like this: 

 

TIMESPEC TS_PCI_BUS = FROM PCI_CLK TO SYS_CLK 10000 ps;

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
38093 ML410 - Known Issues and Release Notes Master Answer Record N/A N/A
AR# 22677
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article