UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22730

LogiCORE PCI Express - Memory Read to Xilinx core is returning all 1s

Description

Some customers have reported that if they send a Memory Read to their user application from the root complex or switch, the core returns all 1s in the completion with data.

Solution

This issue occurs on some systems if the user does not correctly set the Attribute field in the completion with data TLP header. In particular, it seems some systems require the completion to set the value of the No Snoop bit (bit 0 of the two-bit attribute field) to be the same as the No Snoop bit in the original Memory Read TLP. 

 

The problem is not that the core is returning all 1s in the CplD as the data passed by the user is passed unchanged to the link, the issue is that the processor/root is treating the packet as malformed and not passing the data.

AR# 22730
Date Created 09/04/2007
Last Updated 05/19/2014
Status Archive
Type General Article