| AR# | 22733 |
| Part | SW-Floorplanner/PACE |
| Last Modified | 2008-06-17 00:00:00.0 |
| Status | Archive |
| Keywords | 8.1, Floor, planner, PACE, BRAM, MULT |
Keywords: 8.1, Floor, planner, PACE, BRAM, MULT
In PACE and Floorplanner, the LOC constraints for every placement of a MULT/BRAM results in the same location value. Why is this?
Looking at the part in FPGA Editor reveals that the locations are correct (e.g., X0_Y0 - X1_Y15).