UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22753

8.2i XST - XST generates incorrect logic for VHDL code that assigns a bus bit-by-bit

Description

XST generates incorrect logic for VHDL code that assigns a bus bit-by-bit. An example of the incorrect logic is as follows:

output2 <= "001" when sel = '0' else (0 => input(0), others => '0');

output3 <= input when sel = '1' else (1 => input(1), 0 => input(0), 2 => input(2))

Solution

XST cannot correctly process the code the way it is written. You can work around this problem by concatenating the bits as shown below:

output2 <= "001" when sel = '0' else ("00" & input(0)) ;

output3 <= input when sel = '1' else ( input(2)&input(1)&input(0));

Xilinx is investigating this issue; look for this to be fixed in ISE 9.1i.

AR# 22753
Date Created 03/06/2008
Last Updated 12/15/2012
Status Active
Type General Article