When I attempt to generate a Virtex-4 1/2G LogiCORE Fibre Channel Arbitrated Loop v1.1 Core (which was released in 8.1i IP Update #1), the UCF constraint for the refclk_init period is generated with an incorrect period. The UCF specifies a period of 9360 ps, but the correct period should be 4680 ps.
(This issue only affects Virtex-4 cores with 1/2G.)
To fix this problem, change the following line in the 1/2G Virtex-4 UCF:
TIMESPEC "TSclock"= PERIOD "refclk_int" 9360 ps;
TIMESPEC "TSclock" = PERIOD "refclk_int" 4680 ps;