UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22806

8.1i Virtex-4 PAR - Unrouteable signals from BUFR to EMAC clock pin

Description

My design has an EMAC clock driven by a BUFR. I believe that the BUFR is constrained to the correct clock region to successfully route to the EMAC and the Placer does not complain about my constraints. The router fails to successfully route to the EMAC clock pin. When I examine the design in FPGA Editor, I can see that the EMAC is in the same clock region as the BUFR. 

 

Why can't the router make this connection?

Solution

The FPGA Editor view of the EMAC location is misleading. The EMAC clock is routed through the clock region at the top of the PPC hole which is actually two clock regions above where the EMAC appears to be located. 

 

For example, in an xc4vfx60 device, the EMAC site EMAC_X0Y0 appears to be in CLOCK_REGION_X0Y1, but it is actually in CLOCK_REGION_X0Y3. Since a BUFR can only reach loads in the same or vertically adjacent clock region, any BUFR driving an EMAC in site EMAC_X0Y0 must be placed in CLOCK_REGION_X0Y2:CLOCK_REGION_X0Y4. 

 

The version 8.1i clock placer should but does not print a warning when a BUFR is constrained out of reach of an EMAC load. This will be corrected in version 8.2i.

AR# 22806
Date Created 10/22/2008
Last Updated 05/19/2014
Status Archive
Type General Article