This Answer Record outlines release details for the Virtex-4 RocketIO Wizard v1.1.
NOTE: RocketIO Wizard v1.2 is available; see (Xilinx Answer 23897) for details.
Supported Operating Systems
All platforms supported by ISE 8.1i are supported.
1. Ensure that you have an account with Support at Xilinx.com. You can create an account by clicking on the Login link at:
2. Ensure that you have installed ISE 8.1i Service Pack 2 or later. You can download the ISE Service Pack at:
NOTE: Do not interrupt the installation process. During the process, you must accept various pop-up messages. If you have other windows open, the pop-ups might be hidden behind these windows.
Use this method if you are behind a firewall and do not know your proxy settings:
1. Browse to:
2. Click the Download link near the top.
3. Set ISE IP Update for the Download Type.
4. Set 8.1i for the ISE Version.
5. Select the appropriate Operating System.
6. Click Search.
7. Several ZIP files are offered for download.
8. Download all the ZIP files that appear under IP Update.
9. Unzip the ZIP file into the directory representing the installation of ISE 8.1.
10. The unzip step is best done through a utility such as WinZip. If you do not have a ZIP utility, proceed as follows:
In UNIX shell on Linux:
$Xilinx/bin/lin/unzip -d $Xilinx zip-file-name
In a UNIX shell on Solaris:
$Xilinx/bin/sol/unzip -d $Xilinx zip-file-name
In a Windows command prompt:
%Xilinx%/bin/nt/unzip -d %Xilinx% zip-file-name
(In the above, $Xilinx or %Xilinx% represents the location of your ISE 8.1 installation.)
This method is highly automated, but requires you to know your proxy settings if you are behind a firewall.
1. Launch CORE Generator by selecting Start -> Xilinx ISE 8.1 -> Accessories -> CORE Generator from the Windows Start menu.
2. When the CORE Generator GUI opens, select Tools -> Updates Installer from the menu bar. You might need to create a CORE Generator project.
3. CORE Generator displays a warning that it will exit after the installation is complete. Click the Accept button.
4. If you are behind a firewall, a dialog box appears in which you enter the appropriate proxy settings.
5. The IP Updates Installer opens and displays a list of the available IP Update packages that apply to ISE 8.1.
6. You can click the documentation link to acquire more information about each available update.
7. To obtain this release, select ISE 8.1i Virtex-4 RocketIO Wizard 1.1.
8. After making your selections, click Install Selected.
9. The program might indicate that certain other installations are required. Accept these informational dialogs.
10. A dialog might appear asking you to enter your support.xilinx.com User ID and password. Enter the requested information.
11. CORE Generator downloads and installs the requested products and exits.
Launch CORE Generator with suitable project settings and browse to FPGA Features and Design -> IO Interfaces -> RocketIO Wizard 1.1 to verify that the core was correctly installed.
- The ENCHANSYNC signal is no longer floating in the channel bonding example design; it is tied Low in the example. When using channel bonding, tie ENCHANSYNC for the slaves High, and use ENCHANSYNC on the Master to enable or disable the bonding circuit.
- Wizard wrappers for XAUI now more closely match the settings used in the XAUI Core from Xilinx.
- Problems with the mask values generated for multi-byte channel bonding and clock correction sequences have been corrected. In version 1.0, there were cases where the "don't care" settings for a multibyte sequence were ignored.
- The attribute TXSLEWRATE is now set by the wizard based on the slew rate setting for TX in the GUI. In version 1.0, the default setting was always used.
- Loopback is now set correctly in all cases. In version 1.0, there were cases where setting loopback to serial or parallel resulted in a wrapper not configured for loopback.
- The example design now uses positive-edge aligned User Clock signals. This is the current recommended configuration for V4FX MGTs. Version 1.0 aligned the negative edge of USRCLK to USRCLK2.
- Signal widths are corrected for 8-byte interface and 64B/66B cases. In version 1.0, the signal widths for some 8-byte and 64B/66B configurations were set incorrectly.
- The wizard no longer allows FIFO bypass (low latency) modes to be selected with an 8-byte interface. This configuration is not supported by the GT11, but was allowed by version 1.0 of the wizard.
- The wizard no longer allows low latency modes to be selected when using 64B/66B encoding or decoding. These configurations are not supported by the GT11, but were allowed in version 1.0 of the wizard.
- CES4 support has been improved. A new reset block has been added to the example design that implements the reset sequence recommended in UG076 v3.0. In addition, the analog settings used for each configuration have been further optimized based on the settings used for production testing of Virtex-4 FX devices. In version 1.0, CES4 support was limited to calibration block support.
- An additional BUFG has been added to the example design USERCLK divider modules, which employ the PMCD. In version 1.0, a BUFG was used on only one of the two possible clock outputs, which increased the risk of PAR results with excessive skew between user clocks.
- The calculation for User Clock rate with 64B/66B encoding has been corrected.
- The data sheet values for the maximum USRCLK/USRCLK2 rate have been changed since the release of version 1.0 of the wizard. Version 1.1 allows a maximum rate of 250 MHz.
- The TXUSRCLK/TXUSRCLK2 ports of the unused MGT block are now connected to a toggling clock. In version 1.0, these ports were tied to ground.
- The CLK_COR_MIN_LAT/CLK_COR_MAX_LAT settings for PCI Express have been changed to 36 and 44. The settings used in version 1.0, based on preliminary tests, were too low.
- The channel bond limits for several of the protocol files have been corrected. In version 1.0, many of the channel bond limit values were set twice as high as required.
- The default setting for TXDAT_TAP_DAC for CES4 has been changed from 01010 to 10110 to match the new value that will be used for characterization and production testing.
- The CES4 UCF file has been updated to include the UCF command "CONFIG STEPPING = "scd1"". This command was added as a requirement in the most recent errata document for CES4.
- Protocol files for Fibre Channel 1x, 2x, and 4x have been added to the wizard.
- The calibration block for CES2V2/CES3V2 has been upgraded from version 1.2.1 to version 1.2.2.
- The Reference Clock frequency range is limited to between 156.25 MHz and 400 MHz. If anything outside this range is required, then the TXPLLNDIVSEL and RXPLLNDIVSEL values in the MGT wrapper must be manually edited to support them. The reference clock period must also be changed in the example testbench(example_tb.v(hd)).
- The maximum line rate supported in the wizard has been reduced to 6.5 Gb/s based on the top rate of the GT11 after characterization.
- The FX20 part uses a DCM to generate the usrclks from the txoutclk. The DCM_LOCKED signal, which held the user logic in reset until the DCM is locked, was floating for the 4 byte case. This issue has been corrected.
- The VCO upper bound has been reduced to 4.25 GHz.
- 64B/66B options have not been tested in hardware. Devices supporting 64B/66B were not available at development time.
- Multilane protocol files such as XAUI might not turn on all required MGTs in some packages. If your wrapper is missing lanes, re-customize your wrapper and select the needed MGTs on wizard page 2.
- Wizard page 2 (Placement Customization) allows you to select unbonded MGTs on the xc4vfx60 in the ff672 package. MGTs X0Y0, X0Y1, X1Y0, and X1Y1 are not connected to external pins. You should recustomize if you have selected these MGTs and you need to connect them to external logic.
- Configurations using different line rates for TX and RX on the same MGT have not been thoroughly tested, and might not work.
- Example designs for configurations using different data widths for TX and RX might not function.
- Use run lengths supported by your silicon version when selecting "no encoding"/"no decoding" on wizard page 3.
- The example designs provide little support for CRC. The wrapper will configure the CRC blocks, but additional work is required to test and connect the logic.
- Setting the comma alignment (wizard page 4) smaller than the data path width allows incoming data to be aligned to multiple positions. The example design does not account for this and might indicate errors even though data is being received correctly.
- The example design does not currently include blocks to demonstrate Channel Bonding and Clock Correction.
- OOB signaling is not supported in simulation.
- The GT11 SmartModel produces RX Disparity errors due to rounding problems for some reference clock periods. In simulation, if the MGT wrapper locks successfully but shows numerous disparity errors, edit the testbench/example_tb.v(hd) and increment or decrement the REFCLK period by 0.01. For example, in the Fibre Channel 2x and 4x, where the REFCLK period must be changed from 4.71 ns to 4.7 ns.
- The REFCLK drop-down menu is not populated when an MGT line rate greater than 2.125 Gbps and less than 2.488 Gbps is selected. The Wizard does not generate wrappers for these line rates; instead, an error message is displayed regarding the empty REFCLK drop-down menu. This restriction is due to an errata item for Production Step 0 and CES4 devices.