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AR# 22852

8.2i CPLD TSIM - Timing simulation shows undefined signal (X) for register output

Description

Keywords: 8.1i, flip, flop, error

The behavioral simulation functions correctly, but timing simulation results in undefined (X) values for register outputs. No timing errors are reported.

Solution

This is a simulation issue and the hardware is not affected. To work around this issue, open the "*_timesim.vhd" file and assign a default value to the signal "NlwRenamedSignal_GSR," as follows:

signal NlwRenamedSignal_GSR : STD_LOGIC := '0';

You must manually edit this file each time the design is reimplemented because the timing simulation file is recreated.

This issue will be fixed in 8.2i Service Pack 3.
AR# 22852
Date Created 02/06/2006
Last Updated 03/21/2007
Status Archive
Type General Article