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AR# 22856

8.2i ISE - Project Navigator selects Verilog as the default HDL functional Model for schematics and IP Cores, even when the selected simulator supports only VHDL


When creating a new project, ModelSim XE - VHDL is selected. But when a new schematic or IP Core is added, the default HDL functional model is set for Verilog. Project Navigator should look at the simulator setting and use this to set the default functional model or add a second option where I can set what the default is when creating a project.

This will lead to the following load error when attempting simulation:

# XE version supports only a single HDL

# Error loading design


In 8.xi ISE, Project Navigator does not correctly determine the proper functional model in some cases and defaults to Verilog. In this case, the user must select the View HDL Functional Model and/or Simulation Model Target properties and change the value to VHDL.

To change the View HDL Functional Model value:

1. Select the Schematic or IP Core in the Sources window.

2. Then, in the Processes window right-click View HDL Functional Model and select Properties.

3. Change the Functional Model Target Language from Verilog to VHDL.

To change the Simulation Model Target value:

1. Select the Top Level module in the Sources window.

2. Then, in the Processes window, right-click Generate Post-[Place & Route/MAP/Translate/Fit] Simulation Model and select Properties.

3. Change the Simulation Model Target language from Verilog to VHDL.
AR# 22856
Date Created 09/04/2007
Last Updated 07/01/2010
Status Archive
Type General Article