Keywords: XST, process, synthesis, VHDL, status, red x
Although a synthesis process completes without errors, my design fails and Project Navigator reports:
"Process 'Synthesize' failed."
However, there is no indication what the problem is.
This issue occurs in VHDL designs if the entity and architecture names are written in different cases:
entity MY_TOP is
in_a : in std_logic;
in_b : in std_logic;
out_x : out std_logic;
architecture design1 of My_top is
To work around this issue, change the name of either the entity or architecture so that the cases match.
This issue will be fixed in Service Pack 3 for ISE 8.1i, which is scheduled for release in March, 2006.