| AR# | 22863 |
| Part | IP-Processor |
| Last Modified | 2006-02-16 00:00:00.0 |
| Status | Active |
| Keywords | mch_opb_ddr_v1_00_b, mch opb ddr, mch, Processor IP [[EDK sp1]] |
Keywords: mch_opb_ddr_v1_00_b, mch opb ddr, mch, Processor IP
A Burst Read transaction to OPB DDR when bank address boundaries are crossed with the refresh cycle occurring simultaneously causes the Ethernet SGDMA transaction to hang.
The DDR controller hangs while waiting for more RdAcks and RdReq, and it never negates.