Main
Home  :  Support  :  Answers  :  8.1i EDK, OPB DDR - An OPB_DDR test routine fails when the PowerPC cache is enabled

8.1i EDK, OPB DDR - An OPB_DDR test routine fails when the PowerPC cache is enabled

AR# 22865

Search For Another Answer
Topic IP-Processor
Last Updated 02/16/2006
Status Active
Description

Keywords: opb_ddr, opb ddr, processor IP, PowerPC, cache, Central DMA,

My system hangs when a Burst Read is triggered by a Cache Line Read over the PLB2OPB bridge requested by the PowerPC; the system also hangs when the Burst Read is triggered using the OPB Central DMA.

In the MHS, the PARAMETER C_INCLUDE_BURST_SUPPORT = 1 is set.

Solution

This problem has been fixed in core included in the latest EDK 8.1i Service Pack, available at:
http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is EDK 8.1i Service Pack 1.
 
 
/csi/footer.htm