UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22866

8.1i EDK, PLB DDR - The PLB DDR locks up during PLB Indeterminate Burst Read operations

Description

The PLB DDR locks up during PLB Indeterminate Burst Read operations.

Solution

This problem has been fixed in the latest core included in the EDK 8.1i Service Pack, available at: 

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp
The first service pack containing the fix is EDK 8.1i Service Pack 1. 

 

The problem appears to be caused by a memory refresh operation occurring on the last data beat of an ongoing Indeterminate Burst Read. When the DDR controller returns from performing the refresh cycle, it fails to provide the final data and data acknowledge to the IPIF. This situation leads to eventual system lock-up, requiring a reset.

AR# 22866
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article