LogiCORE PCI Express - What is the Maximum Payload Size (MPS) value of the PCI Express core? What does the MPS do?
Description
Keywords: MPS, maximum, payload, TLP
What is the Maximum Payload Size (MPS) setting of the PCI Express and PCI Express PIPE cores?
For what is MPS used, and how is this value set?
Solution
What is MPS?Maximum Payload Size defines the maximum TLP (Transaction Layer Packet) data payload size for the device. As a receiver, a device must be able to handle inbound TLPs with payloads as large as the set value. As a transmitter, the device should not create TLPs with data payloads larger than the MPS setting.
How is the MPS value of a device set?
The device advertises its MPS value through the Device Capability Register. The Device Capability Register is defined in section 7.8.3 of the PCI Express Base Specification v1.1. The devices capable MPS is set by bits [2:0] of Device Capability Register.
Defined encoding for this field is:
000b 128 bytes max payload size
001b 256 bytes max payload size
010b 512 bytes max payload size
011b 1024 bytes max payload size
100b 2048 bytes max payload size
101b 4096 bytes max payload size
Once the system powers up, the root complex will evaluate the various MPS settings of the Device Capability Registers in the system. It will then write the MPS value the device must use into the Device Control Register. The Device Control Register is defined in section 7.8.4 of the PCI Express Base Specification v1.1. The MPS setting is bits [7:5] and has the same encodings as above. Once set, the device must not generate TLPs with payload sizes larger than this value and must be able to accept TLPs with payload sizes up to this value.
How do I know the value of the MPS setting in the Device Control Register?
The user application interface has an output port called cfg_dcommand[15:0]. Bits [7:5] of this output bus inform you of the MPS setting in the Device Control Register.
What are the maximum MPS values supported by the Xilinx PCI Express and PCI Express PIPE cores?
Core..............................................................MPS Capability
pci_exp_1_lane_32b_ep...............................512 Bytes or 010b
pci_exp_4_lane_32b_ep...............................512 Bytes or 010b
pci_exp_8_lane_64b_ep...............................256 Bytes or 001b
pci_exp_1_lane_64b_ep...............................512 Bytes or 010b
pci_exp_4_lane_64b_ep...............................512 Bytes or 010b
pci_exp_1_lane_epipe_ep............................512 Bytes or 010b
The maximum MPS value allowed in PCI Express is 4096 bytes. Why does the core not support up to 4096 bytes?
As the supported MPS size increases, so does the amount of memory and logic required to process the packets. Currently most if not all devices available on the market support 256 byte MPS values or less. It is important to note that the MPS value used on a given link is equivalent to or less than the lowest MPS setting in either link partner's device capability register. For example, if you have a Xilinx core with an MPS of 512 bytes communicating with another vendor's device with a MPS of 128 bytes, the MPS for the link will be 128 bytes.
Xilinx continually monitors new devices entering the market; once other vendors support larger payloads, the Xilinx core will be adjusted as necessary. No extra logic and memory will be added until it is required.
How do I change the MPS setting for the Device Capability Register?
This is done in the CORE Generator GUI. You can select any allowable value for MPS up to the maximum MPS setting allowed for the core in use. The maximum MPS settings for each core are shown above. For example, if you are targeting a pci_exp_4_lane_32b_ep, legal values are 512 bytes, 256 bytes, or 128 bytes.