Keywords: NGDBuild, 455, custom IP
When I add a self-designed peripheral to an EDK project, many of the ports generate multiple driver errors similar to the following:
"ERROR:NgdBuild:455 - logical net 'rgg_0_GPS_1PPS_IBUF' has multiple driver(s):
pin O on block ibuf_77 with type IBUF,
pin PAD on block rgg_0_GPS_1PPS_IBUF with type PAD
ERROR:NgdBuild:462 - input pad net 'rgg_0_GPS_1PPS_IBUF' drives multiple
buffers:
pin I on block obuf_81 with type OBUF,
pin I on block rgg_0/rgg_0/USER_LOGIC_I/onepps_input/ASYNC_IN_IBUF with
type IBUF
... "
These errors can occur when the netlists created are synthesized with the option to include I/O buffers. The default option for XST is "Add I/O buffers". If all of the I/O signals for this block already have IBUFs and OBUFs, when you try to include the block into the EDK design, PlatGen places additional I/O buffers. The errors will then occur because there are two sets of buffers (multiple drivers).
To work around this issue, uncheck the option and resynthesize the design, as follows:
1. Open your IP project in ISE.
2. Right-click on Synthesize - XST.
3. Select Properties.
4. Select Xilinx Specific Options.
5. Deselect Add I/O Buffers.
6. Select OK.
7. Resynthesize your design.