After I downloaded the XAPP901/UG096 reference design to the development board, it would not execute or was unreliable.
This solution is applicable for both EDK 7.1 and EDK 8.1.
The reference design uses a 300 MHz output (CLKFX) from dcm_0 to clock the PowerPC. The C_DFS_FREQUENCY_MODE parameter of that DCM (dcm_0) should be set to HIGH. This is not done automatically by Base System Builder. The change can be done via Platform Studio in the add/edit cores dialog box or in the MHS file directly.
This change is needed for the reference design to work reliably.
Please refer to (Xilinx Answer 21936) for additional information.