I receive the following error when running "Generate Netlist" in XPS. What does it mean? Are square brackets supported?
"INFO:MDT - It is invalid to splice a signal into smaller signals using
Use signal concatenation (&) operator or util_bus_split IP instead
Following is invalid syntax
PORT A = mysig # a 2-bit signal
PORT B = mysig # invalid syntax 
PORT C = mysig
Please use the following syntax
PORT A = mysig_0 & mysig_1
PORT B = mysig_0
PORT C = mysig_1"
To splice a bus signal into smaller signals or to access individual bits of a bus, the concatenation (&) operator or util_bus_split peripheral must be used in the MHS. Vector slicing or splicing by means of only square brackets was never intended to be supported syntax. Starting in EDK 8.1i, PlatGen DRCs have been improved to catch the illegal use of square brackets in the MHS file.
Please refer to MHS->Design Considerations->"Concatenation" section of the Platform Specification Format manual available at:
for more information on the concatenation operator.
Documentation on the bus split utility can be found in the EDK install directory (that is, "E:\EDK81\hw\XilinxProcessorIPLib\pcores\util_bus_split_v1_00_a").