We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22918

LogiCORE PCI - What is the difference in the pcim_top.v(.vhd) and pcim_top_r.v(.vhd) files?


Two top-level files called pcim_top.v(.vhd) and pcim_top_r.v(.vhd) are located in the /src/xpci and /example/source directories of the PCI core files. What is the difference between these files and how should they be used?


The pcim_top_r.v(.vhd) file should be used for Virtex-4 PCI core designs. This file contains an input port for the IDELAY controllers used in Virtex-4 designs. This is a 200 Mhz clock input and the port is called JCL. Note that this clock can be generated internal to the design; if this is the case, this port can be removed. 


The pcim_top.v(.vhd) file is used for all other non-Virtex-4 PCI core designs.

AR# 22918
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article