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AR# 22937

MIG 1.5 - Release Notes for Memory Interface Generator (MIG)

Description

This Answer Record contains the Release Notes for ISE 8.1i MIG 1.5, and includes the following:

- Supported Operating Systems

- Software and Tool Requirements

- Installation Instructions

- Getting Started

Solution

New or Modified Cores in This Release

- MIG 1.5 Memory Interface Generator for Virtex-4 and Spartan-3/-3E devices

Supported Operating Systems

- Windows XP Home (Service Pack 1)/Professional (Service Pack 1) (32 bit)

- MIG is not available on other ISE platforms

Xilinx Design Tools Version Requirements

To use this IP Update, first ensure that you have installed ISE 8.1i with Service Pack 1 (8.1i.01i).

You can obtain ISE 8.1i Service Packs from the Download Center at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

MIG 1.5 requires ISE 8.1i IP Update 1 or later. If it has not already been installed, IP Update 1 is automatically installed by the Updates Installer before the ISE 8.1i MIG 1.5 IP Update is installed. See (Xilinx Answer 22155 ) for issues related to ISE 8.1i IP Update 1.

Acrobat Reader Version 5 or later must be installed. You can download the latest Acrobat software from the Adobe Web site at:

http://www.adobe.com/products/acrobat/readstep.html

Installation

Method 1

Use this method if you are behind a firewall and do not know your proxy settings.

1. Ensure that you have the latest ISE 8.1i Service Pack and the latest IP Update from the Download Center at:

http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp

- For ISE, you will receive an installer.

- For the IP Update, you will receive a ZIP file that you must unzip into the 8.1i installation.

- For MIG 1.5, ISE 8.1i sp1 and the latest IP Update are required.

2. If you are not registered for the Memory Corner, register at:

http://www.xilinx.com/xlnx/xil_entry2.jsp?sMode=login&group=memory_customers

3. Download the MIG 1.5 from:

http://www.xilinx.com/support/software/memory/protected/ise_81i_mig_v1_5.zip
(Enter your xilinx.com account name and password when prompted.)

4. Unzip this file into the root ISE 8.1i installation (C:\Xilinx by default).

Method 2

1. Launch CORE Generator by selecting Start -> Xilinx ISE 8.1i -> Accessories -> CORE Generator from the Windows Start menu.

2. When the CORE Generator GUI opens, select Tools -> Updates Installer.

3. CORE Generator displays a dialog box with a warning indicating that it will exit after the installation is complete. Click Accept.

4. CORE Generator connects you to www.xilinx.com and might ask for your xilinx.com User ID and password. If you are behind a firewall, you might have to enter the appropriate proxy settings.

5. The IP Updates Installer dialog box opens and displays a panel listing the available updates.

6. Select "ISE 8.1i MIG 1.5" and click the Install Selected button. The program might indicate that other installs are required. You can accept these informational messages. CORE Generator downloads and installs the requested products and exits.

NOTE: Do not interrupt the installation process. During the process, you must accept various pop-up messages. If you have other windows open, the pop-ups might be hidden behind these windows.

Getting Started

To launch MIG, follow these steps:

1. Launch CORE Generator by selecting Start -> Xilinx ISE 8.1i -> Accessories -> CORE Generator.

2. Create a CORE Generator project.

3. Set your Xilinx part correctly; it cannot be changed inside MIG. Note that Virtex-4 and Spartan-3/-3E devices are supported by MIG.

4. Remember the location of the CORE Generator project directory. The "View by Function" tab to the left shows the available cores organized into folders.

5. Launch MIG by selecting Memories & Storage Elements -> MIG -> Memory Interface Generator.

6. In the Module Name text box, enter the name of the module to be generated. When you click Generate, the module files are generated in a directory with the same name as the module name in the CORE Generator project directory.

7. After generation, close the GUI by selecting the Dismiss button.

The "Generated IP" tab to the left lists your generated modules. You can use the generated "ise_flow.bat" script or the ISE GUI to manually add the generated HDL files to a project. The MIG User Guide explains how the generated HDL files are used. You can access the MIG User Guide from the View Data Sheet links in CORE Generator, or from the Data Sheet button in the MIG GUI.

Additional Information

You can access additional MIG and memory-related information at:

http://www.xilinx.com/products/design_resources/mem_corner/index.htm

NOTE: To access this URL, you must register specifically for the Memory Interface Generator product.

See Memory Interface Generator (MIG) under the "Resources" section.

You can search for other available IP cores at:

http://www.xilinx.com/xlnx/xebiz/search/ipsrch.jsp

If you have comments, questions, or problems, contact Xilinx Technical Support at:

http://www.xilinx.com/support/techsup/tappinfo.htm

What's New in MiG 1.5?

Features and Changes

All DDR1 and DDR2 Designs:

* Tool frequency bar now indicates the min and max of both design and memory frequencies. For a selected memory part, frequency depends on the CAS latency also. MIG1.5 tool does not consider the CAS latency while displaying the frequency. You should set the design frequency as per the selected CAS latency. This is a common issue for all Spartan-3 and Virtex-4 designs.

* All V4 interfaces that use FIFO16 may not work.

All Spartan-3 and Spartan-3E

NOTE: A bug was fixed in the algorithm for assigning pins for Spartan-3 and Spartan-3E. MIG 1.5 designs are correct, but in some cases might not match the pin-out created by earlier releases.

Spartan-3 and Spartan-3E DDR1

*Added CAS latency 2 and 2.5

*Added burst length 2 and 8

*More memory components added (see tool for specifics)

*Added Registered DIMMs

*Added more unbuffered DIMMs

*Added more SODIMMS

*Ability to not add DCM and test bench

*Programmable mode register support

*Outputs a sample simulation folder for fixed configuration; also outputs sim folder for one of the board configurations.

*ISE 8.1i support only

*NOTES:

---For Spartan-3E Step0 devices, users should correct the tool output to set the correct frequency. Max. freq. of Step 0 devices is only 90 MHz.

---Max delay constraints in ucf file are generated according to frequency.

---In MIG1.4 release, DCM and SYS_CLK were not locking to the same bank in some cases. This bug has been fixed.

---cal_ctl.vhd modified similar to cal_ctl.v module to simplify timing

---DDR1-SP3 with Precision - When ChipScope inserted, local clock routes were taking wrong paths.

---With the SL361 and the frequency set to 166 MHz using components, the expected behavior is: XST has clean timing. Synplicity VHDL has clean timing. Synplicity Vlog has 330 ps slack. Precision VHDL has 433ps and Prec. Verilog has 204 ps slack.

---With the SL361 and the frequency set to 166 MHz using DIMMs, the expected behavior is: XST Verilog has clean timing, XST VHDL has 740ps Slack. Synp. Verilog has clean timing, Synp. VHDL has 800 ps Slack.

Spartan-3 DDR2

*Added Synplicity Synplify 8.2 support

*Added burst length 8

*Added programmable mode register support

*Added more components (see tool for further information)

*Added registered DIMMs

*Added unbuffered DIMMs

*Outputs a sample simulation folder for fixed configuration

Virtex-4 DDR1

*Added Synplicity Synplify 8.2 support

*Added CAS latency 2 and 2.5

*Added burst length 2 and 8

*Added more components (see tool for further information)

*Added more registered DIMMs (see tool for further information)

*Removed need for loopback read enable external signal

*Added programmable mode register support

*Added option to use clock-capable pins for strobes for maximum design flexibility

*Added support for interleaved column address

*Changed to frequency-dependent memory timing parameters

*For one of the hardware configurations, a sim folder has been provided with board files

*NOTES:

---The Virtex-4 DDR SDRAM design supports only byte wise masking of the memory data because of the limitation of the internal block RAM.

---For 1Gb devices, the models were available for only -6T devices. Therefore, only the -5B design is functionally verified using the 133 MHz clock.

---The DDR SDRAM Virtex4 designs before MIG1.4 used externally normalized READ enable signals to capture the valid data internally. In MIG1.5, after initialization process, internally it performs some dummy write operations. After dummy writes, it issues a read command to read the data back from memory. When the read command is given during the dummy phase, it increments the counter until the read data matches with the dummy data. This count value is the delay between the read command and the read enable assertion for normal read operation. The read enables are now generated internally on the basis of number of banks and the number of data bits allocated in that bank. The design uses one DQS per bank and the corresponding DQ bits to generate the read enables that captures the valid data in the internal block RAM.

---The frequency bar on the GUI changes according to the speed grade of the memory device selected. Set the frequency manually according to the CAS latency also. Example, for memory speed grade of 5 and CAS Latency of 2, frequency set should not be more than 133 MHz. Make sure of this.

---For running the design below 100 MHz frequency, you should set the DCM attributes as follows:

------attribute DLL_FREQUENCY_MODE of DCM_BASE0 : label is "LOW"; Set to HIGH for frequencies above 100 MHz

------attribute DCM_PERFORMANCE_MODE of DCM_BASE0 : label is "MAX_RANGE"; for Low frequency, set to MAX_RANGE; for frequency above 100 MHz, set it to MAX_SPEED

---While manually assigning the pins to the DQS and the DQ pins, allocate the DQS and its corresponding data bits in the same bank.

---There is an issue in FIFO full status generation with FIFO16s for V4 series of FPGAs. Sometimes, the FIFO full status is not generated, even though FIFO is full. To work around this issue, use external logic to generate the FIFO full status or use the COREGen BRAM FIFO. This will be implemented in MIG1.6. See (Xilinx Answer 22462) for more information.

Virtex-4 DDR2 Direct Clocking

*Added Synplicity synthesis - v8.2

*Low frequency improvements allow the design to function below 135 MHz

*Improved startup performance after reset

*Changed to frequency-dependent memory timing parameters

*Added option to use clock-capable pins for strobes

*Removed need for loopback read enable external signal

*For one of the hardware configurations, a sim folder has been provided with board files

*NOTES:

---The DDR SDRAM Virtex-4 designs before MIG1.4 used externally normalized READ enable signals to capture the valid data internally. In MIG1.5, after the initialization process, internally it performs some dummy write operations. After dummy writes, it issues a read command to read the data back from memory. When the read command is given during the dummy phase, it increments the counter until the read data matches with the dummy data. This count value is the delay between the read command and the read enable assertion for normal read operation. The read enables are now generated internally on the basis of number of banks and the number of data bits allocated in that bank. The design uses one DQS per bank and the corresponding DQ bits to generate the read enables that capture the valid data in the internal block RAM.

---In no DCM case, the user is expected to drive the clocks through different buffers and through BUFGs to make sure the tools retain the clocks.

---There is an issue in FIFO full status generation with FIFO16s for V4 series FPGAs. Sometimes, the FIFO full status is not generated even though FIFO is full. The work around for this is to use external logic to generate the FIFO full status or use the COREGen BRAM FIFO. This will be implemented in MIG1.6. See (Xilinx Answer 22462) for more information.

Virtex-4 DDR2 SERDES (New!)

*New design technique added. For more information, see: (Xilinx XAPP721): "High-Performance DDR2 SDRAM Interface Data Capture Using ISERDES and OSEDES" and (Xilinx XAPP723): "DDR2 Controller (267 MHz and above) Using Virtex-4 Devices."

*Allows higher operating frequency than above direct clocking technique but is more restrictive on pin placement and has slightly higher latency.

*Synthesis: XST and Synplicity Synplify 8.2

*CAS latency: 4, 5

*Burst length: 4, 8

*Additive latency: 0, 1, 2

*Components only (no DIMM support yet)

*Outputs a sample simulation folder for fixed configuration

*Does not use a loopback read enable

*Uses frequency-dependent timing parameters

*Sim folders were provided with board files

*NOTES:

---Sometimes, the tool is not allocating DCM and PMCD on the same side. Make sure that both DCM and PMCD are placed on the same side. If they are not placed on the same side, it is necessary to constrain them in the ucf file.

---There was a simulation error with VHDL oserdes unisims, verilog oserdes unisims used to run simulations.

Virtex-4 RLDRAM II

*Added option to use clock-capable pins for strobes for maximum design flexibility

*Added Synplicity synthesis support

*For one of the hardware configurations, a sim folder has been provided with board files

*NOTES:

---For some cases of RLDRAM2 designs, the following warnings were flagged on DCMs.

WARNING:PhysDesignRules:372 - Gated clock. Clock net DCM_AUTOCALIBRATION_infrastructure_top0/clk_module0/DCM_BASE0/DCM_ADV/infrastructure_top0/clk_module0/DCM_BASE0/DCM_ADV/clk(7) is sourced by a combinatorial pin. This is not good design practice. Use the CE pin to control the loading of data into the flip-flop.

See (Xilinx Answer 21435) for more information.

Virtex-4 QDR II SRAM / DDR II SRAM

*Added option to use clock-capable pins for strobes for maximum design flexibility

*Added Synplicity Synplify 8.2 synthesis support

*For one of the hardware configurations, a sim folder has been provided with board files

*NOTES:

---There is an issue in FIFO full status generation with FIFO16s for V4 series FPGAs. Sometimes the FIFO full status is not generated, even though the FIFO is full. To work around this issue, use external logic to generate the FIFO full status or use the COREGen BRAM FIFO. This will be implemented in MIG1.6. See (Xilinx Answer 22462) for more information.

Supported devices

*All Virtex-4 devices in all packages

* All V4 interfaces that use FIFO16 may not work.

*Most Spartan-3 devices are supported

---XC3s50 and xc3s200 are not supported, as there are not enough pins to create a 16-bit interface.

Software Support

*ISE 8.1.1i is required. No other versions have been tested.

Other NOTES:

*The first version of the feature has been added to verify externally generated UCF's for memory interface designs.

---"Verify my ucf" does not work for "use Clock capable pins for strobes/read clocks." In other words, the tool currently does not verify whether clock-capable pins are used for strobes/rd clks.

*"Stepping" is not handled by MIG. This is true for S3E and V4 devices that have new "steppings."

*The Users Guide is located at "%XILINX%\coregen\ip\xilinx\other\com\xilinx\ip\mig_v1_5\data\fpga_tlib."

To disable the FIFO16 warning, see (Xilinx Answer 22999).

AR# 22937
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article