We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 22994

9.2i EDK, Spartan-3E Starter Kit - "ERROR:Place:848 - Automatic clock placement failed"


When I create a Base System Builder (BSB) design for the Spartan-3E Starter Kit, the following error message occurs:

"ERROR:Place:848 - Automatic clock placement failed. Please attempt to analyze the global clocking required for this design and either lock the clock placement or area locate the logic driven by the clocks so that the clocks may be placed in such a way that all logic driven by them may be routed. The main restriction on clock placement is that only one clock output signal for any competing Global / Side pair of clocks may enter any region. For further information see the "Quadrant Clock Routing" section in the Spartan-3 E Family Data Sheet."


There are three methods you can use to work around this problem:

- Use the dcm_v1_00_a Core instead of the dcm_v1_00_b Core.

- Use the MAP -timing switch. This switch turns on when the Xplorer Script is used:

1. In XPS, select Project > Project options.

2. Select Hierarchy and Flow tab.

3. Select Xplorer Scripts from the Effort Level to Run FPGA Implementation Tools pull-down menu selection.

4. Select OK.

- Manually lock down the DCMs and BUFGs using the "loc" constraint. To accomplish this, an analysis of the design is needed to determine which quadrant to use for the DCMs and BUFGs.

For information on Spartan-3E, refer to the Spartan-3E user guides found at:


For information on using constraints, please refer to the Constraints Guide found at: http://www.xilinx.com/support/software_manuals.htm

This problem will be fixed in a future release of ISE.

AR# 22994
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article