How does the PM_STAT[47:0] output signal from the PCI-X Core map to Power Management registers?
The PCI-X Core supports the Power Management Register Block as shown in Figure 3-3 of PCI Bus Power Management
Interface Specification v1.2. This register is also shown here:
The PM_STAT47:0] Core output signal is mapped to the Power Management Register Block as follows:
PM_STAT[47:40] - Data
PM_STAT[39:32] - PMCSR_BSE Bridge Support Extensions
PM_STAT[31:16] - Power Management Control/Status Register (PMCSR)
PM_STAT[15:0] - Power Management Capabilities (PMC)