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AR# 23001

LogiCORE PCI-X - How does the PM_STAT[47:0] output signal map to Power Management registers?

Description

How does the PM_STAT[47:0] output signal from the PCI-X Core map to Power Management registers?

Solution

The PCI-X Core supports the Power Management Register Block as shown in Figure 3-3 of PCI Bus Power Management 

Interface Specification v1.2. This register is also shown here: 

 

Power Management Register Block
Power Management Register Block
 

 

The PM_STAT47:0] Core output signal is mapped to the Power Management Register Block as follows: 

 

PM_STAT[47:40] - Data 

 

PM_STAT[39:32] - PMCSR_BSE Bridge Support Extensions 

 

PM_STAT[31:16] - Power Management Control/Status Register (PMCSR) 

 

PM_STAT[15:0] - Power Management Capabilities (PMC)

AR# 23001
Date Created 03/12/2008
Last Updated 05/20/2014
Status Archive
Type General Article