How does MS_STAT[95:0] output signal from the PCI-X Core map to Message Signaled Interrupt registers?
The PCI-X core supports the 64-bit Message Address MSI capability structure. For more information on the MSI capability structure, see section 6.8.1 of the PCI Local Bus Specification v3.0.
The 64-bit message address capability structure is shown here:
The MS_STAT[95:0] output of the core is mapped to the message address capability structure as follows:
MS_STAT[95:80] = Message Control
MS_STAT[79:64] = Message Data
MS_STAT[63:32] = Message Upper Address
MS_STAT[31:0] = Message Lower Address