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AR# 23006

Embedded Tri-mode Ethernet MAC Wrapper v4.1 - GMII_COL/MII_COL not connected correctly in V4 Ethernet MAC Wrappers


If I select the Tri-Speed GMII or MII configurations of the Virtex-4 Ethernet MAC (4.1)Wrappers (in both VHDL and Verilog), there is a mistake in the connection of signals in the "<component_name>_top" file, where <component_name> is what I have typed into the component name box in the GUI. EMAC0 and EMAC1 are both affected. The signals that are connected to the GMII_COL_{0 or 1} or MII_COL_{0 or 1} ports of the <component_name> sub-module have the wrong names.


A patch is available to fix this issue. See (Xilinx Answer 22332) to download the patch. 
To work around this issue in the GMII case, please change the signals that connect to the GMII_COL_# input of the <component_name> block from gmii_col_int_# to gmii_col_#_i. In the MII case, please change the signals that connect to the MII_COL_# input of the <component_name> block from mii_col_int_# to mii_col_#_i. # is the number of the EMAC, i.e., 0 or 1.  
For example, for a Verilog GMII MAC, you will get: 
".GMII_COL_0(gmii_col_int_0)," and/or ".GMII_COL_1(gmii_col_int_1),"  
Where it should be: 
".GMII_COL_0(gmii_col_0_i)," and/or ".GMII_COL_1(gmii_col_1_i),"  
The MII interface is similarly wrong: 
".MII_COL_0(mii_col_int_0)," and/or ".MII_COL_1(mii_col_int_1),"  
Should be: 
".MII_COL_0(mii_col_0_i)," and/or ".MII_COL_1(mii_col_1_i),"  
This issue will be fixed in ISE 8.2i IP Update 1.
AR# 23006
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article