My design uses only about 50 percent of the slice resources in the device, but PAR is unable to route the design. What causes this situation?
Several cases have been observed where low-utilization designs with many high-fanout nets fail to route successfully. An examination of the placement results in FPGA Editor reveals that PAR's placement algorithms are not well tuned for this sort of design. A characteristic of this problem is that most slices will be placed in the center of the device in a circular pattern and the corners of the device will be virtually unoccupied.
NOTE: It is important to ensure that global buffers are assigned to all eligible high-fanout nets (clocks and S/R signals) before assuming that routing congestion is resulting from the placement issues described in this Answer Record.
A placer enhancement is scheduled for version 10.1i to address this problem. The placer will recognize the characteristics of a problem design and make algorithmic adjustments that will allow the resulting placement to be spread out in a less congested manner.
Meanwhile, this problem can be avoided by area constraining the design to force a placement that is spread out more. One way to do this effectively is to constrain each of the clock domains in the design to a unique group of clock regions in the device. The following is an example of UCF constraints used to constrain three clock domains to three groups of clock regions:
NET "clk1" TNM_NET = "TNM_clk1" ;
TIMEGRP "TNM_clk1" AREA_GROUP = "AG_clk1" ;
AREA_GROUP "AG_clk1" RANGE = CLOCKREGION_X0Y4,CLOCKREGION_X0Y5,CLOCKREGION_X0Y6,CLOCKREGION_X0Y7 ;
AREA_GROUP "AG_clk1" RANGE = "RAMB16_X0Y0:RAMB16_X5Y27" ;
NET "clk2" TNM_NET = "TNM_clk2" ;
TIMEGRP "TNM_clk2" AREA_GROUP = "AG_clk2" ;
AREA_GROUP "AG_clk2" RANGE = CLOCKREGION_X1Y4,CLOCKREGION_X1Y5,CLOCKREGION_X1Y6,CLOCKREGION_X1Y7 ;
NET "clk3" TNM_NET = "TNM_clk3" ;
TIMEGRP "TNM_clk3" AREA_GROUP = "AG_clk3" ;
AREA_GROUP "AG_clk3" RANGE = CLOCKREGION_X0Y0,CLOCKREGION_X0Y1,CLOCKREGION_X0Y2,CLOCKREGION_X0Y3,CLOCKREGION_X1Y0,CLOCKREGION_X1Y1,CLOCKREGION_X1Y2,CLOCKREGION_X1Y3 ;
Note that for the "clk1" clock domain, the slices were restricted to four clock regions, but the BLKRAM was given use of the entire device.
After making a first pass at partitioning the design, examine the area group summary in the MAP report (.mrp) and the resulting placement in FPGA Editor. The goal is to spread the slice logic throughout the device without creating any local areas of congestion. The number of clock regions and their locations can be adjusted for each clock domain until a good balance is found.