In the v7.4 Core, the DPA circuit is supposed to automatically monitor the READY signal form IDELAYCTL, but it does not.
The Sink core might be able to complete the phase alignment (PhaseAlignComplete = 1) and also might go in frame (SnkOof=0), but the DPA might choose the bad sampling point, and it will report DIP4 errors.
You must modify your startup sequence to wait for 5 us or add a mechanism to monitor the ready of IDLAYCTL.
See (Xilinx Answer 16176), which will contain the revised startup sequence requirement.
If you have installed the v7.4 patch mentioned in (Xilinx Answer 23155), it is not necessary to wait for the ready signal form IDELAYCTL.