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AR# 23075

LogiCORE FIFO Generator - What is the actual depth of the FIFO?


What is the actual depth of the FIFO generated by COREGen?


The effective depth will vary depending on the type of FIFO you generate.

For common clock FIFOs:

The depth you select is the actual depth you will receive in common clock case.

For independent clock FIFOs (Block Mem, Dist Mem type):

In the case of independent clocks, the physical depth of the FIFO you are receiving is actually the depth you have selected. However, the usable depth is always one less. At any given time, one location is not used in order to prevent the write_pointer and the read_pointer (internal pointers) from overlapping. If these two pointers were to overlap, you will not be able to determine if the FIFO is actually EMPTY or FULL. For this reason, the usable depth is always one less. You can think of FIFO as a circular buffer.

For FIFO16 (common of independent clocks):

In the built-in FIFO case, several FIFO16 primitives are cascaded together to form the desired depth. Since we need to account for the latency of the Full flag from each of these primitives, we are using ALMOSTFULL flags from each of these primitives for the generation of the FULL flag of the core. Therefore, with each of the primitives used, you will loose about 5 usable locations.

The last page of the FIFO Gen GUI is the summary page, and it will indicate the actual usable depth.

AR# 23075
Date 12/15/2012
Status Active
Type General Article
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