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AR# 23084

8.1i CORE Generator - Why is my core implemented as 0 Slices (0 LUTs and 0 Flip-flops) when I am using a core that has a structural model?

Description

Keywords: structural, missing, stripped, removed, zero, IP, core, UniSim, model, Verilog, hdl

Why is my core implemented as 0 Slices (0 LUTs and 0 Flip-flops) when I am using a core that has a structural model?

Solution

This can happen if Verilog is selected as the HDL language for core processing ("View HDL Functional Model" language setting) and a structural model is written out for the IP core.

There are 2 ways to resolve this problem.

You can change the HDL file that Project Navigator is using for synthesis from Verilog to VHDL:
1. Select the Core XCO file in the Project Navigator "Sources for Synthesis/Implementation" window.
2. Right-click on the "View HDL Functional Model" in the Project Navigator "Processes" window and select "Properties".
3. Change the "Functional Model Target Language" to "VHDL".
4. Press "OK" and re-implement the design.

You can add the necessary BlackBox attributes to the generated Verilog file so that the Synthesis tool will treat the core as BlackBox.
1. Open the <CORENAME>.v file, where <CORENAME> is the name of the IP you generated.
2. Add the following Black Box attributes to the end of the Verilog File:

// XST black box declaration
// box_type "black_box"
// synthesis attribute box_type of test is "black_box"

3. Save the updated file and implement design again.

This issue is resolved in ISE 8.1.01i.
AR# 23084
Date Created 02/14/2008
Last Updated 03/04/2008
Status Archive
Type General Article