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AR# 23108

8.1i SP2 Virtex-4 PAR - Regional Clock Placer creates unrouteable placement


I have upgraded to ISE version 8.1i sp2, and now one of the Regional Clocks in my design has failed to route. What causes this and how can I work around the problem? 


A case has been experienced where the Secondary Clock Placer (which automatically range constrains Regional Clock domains) failed to properly constrain all of the clock loads, leading to unroutable connections. The hardware limitations on Regional Clocks are: 


- A Regional Clock can only drive loads in the same, or vertically adjacent, Clock Region. 

- No more than two Regional Clocks can drive loads within a particular Clock Region. 


If the Secondary Clock Placer fails to control these two limitations, an unroutable configuration results.


This problem will be fixed in version 8.2i. Meanwhile, this problem can be corrected by adding a UCF constraint to control the placement of the clock domain that is not being automatically constrained properly:  


NET "zkprctrl/zl_fx_xc_core_0/xdr_se_io_0/xdr_pad_clkin_r" TNM_NET = "TNM_clk1" ; 

TIMEGRP "TNM_clk1" AREA_GROUP = "AG_clk1" ; 



NOTE: It is helpful to view the failed placement in FPGA Editor to examine the Regional Clock placement. The editor has the ability to display a Clock Region layer in 8.1i.

AR# 23108
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article