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AR# 23117

10.1 NetGen, Timing Simulation - Why do I receive false setup and hold checks in my X_FF design that utilizes the fast carry paths in Virtex-4?

Description

Why do I receive false setup and hold checks in my X_FF design that utilizes the fast carry paths in Virtex-4?

Solution

This is caused by NetGen and TRACE mismatches on the delay calculations. In the Virtex-4 device, there are four fast carry paths in which NetGen and TRACE do not match. Xilinx is aware of this problem and is working on a fix for it. To fix this issue so that all of these paths match is a significant amount of work and is being solved in increments. Xilinx has identified that the most commonly used path is the CARRYIN to CARRYOUT path, which is predominantly used in DSP designs.  

 

Xilinx plans on a solution for the CARRYIN to CARRYOUT path timing discrepancy in future releases of ISE.

AR# 23117
Date Created 09/04/2007
Last Updated 05/20/2014
Status Archive
Type General Article