| AR# | 23158 |
| Part | EDK_simgen |
| Last Modified | 2006-03-29 00:00:00.0 |
| Status | Active |
| Keywords | ModelSim, Cache, EDK, MicroBlaze, simulation |
Keywords: ModelSim, Cache, EDK, MicroBlaze, simulation
When I run MicroBlaze with the cache enabled, the following error occurs:
"# ** Error: Memory Collision Error on RAMB16_S9_S9: :tb:dut:uproc:microblaze_0:microblaze_0:using_dcache:dcache_i1:old_cache_scheme:using_fpga:using_18kb_brams:gen_tag_bram(1):tag_use_s9:ramb16_s9_s9_1: at simulation time 74999667 ns.
# A read was performed on address 05a (hex) of port A while a write was requested to the same address on Port B The write will be successful however the read value is unknown until the next CLKA cycle
# Time: 74999667 ns Iteration: 5 Instance: /tb/dut/uproc/microblaze_0/microblaze_0/using_dcache/dcache_i1/old_cache_scheme/using_fpga/using_18kb_brams/gen_tag_bram__1/tag_use_s9/ramb16_s9_s9_1"