MAP failed for my design withthe following message about a timing constraint being impossible to meet. What does this mean and why did MAP failbefore any attempt was made to Route the design?
"ERROR:Pack:1653 - At least one timing constraint is impossible to meet because component delays alone exceed the constraint. A timing constraint summary below shows the failing constraints (preceded with an Asterisk (*)). Please use the Timing Analyzer (GUI) or TRCE (command line) with the Mapped NCD and PCF files to identify which constraints and paths are failing because of the component delays alone. If the failing path(s) is mapped to Xilinx components as expected, consider relaxing the constraint. If it is not mapped to components as expected, re-evaluate your HDL and how synthesis is optimizing the path. To allow the tools to bypass this error, set the environment variable XIL_TIMING_ALLOW_IMPOSSIBLE to 1."
This error message is an indication that there are timing constraints where the block delays alone exceed the constraint making it impossible for the Router to add delay and meet the constraint. The intent is to stop processing as early as possible rather than waste time on an impossible task. An NCD file is written for timing debug purposes. This NCD file should not be used for any purpose than to investigate the impossible timing issue. Since processing stopped before the design was fully packed and placed, it's not uncommon for"overmapped" messages to appear in the mapping report (.mrp) even though the design utilization isn't very high. The error message can be bypassed and a fully optimized design generated by setting the following environment variable:
setenv XIL_TIMING_ALLOW_IMPOSSIBLE 1
For general information about setting ISE software environment variables, see (Xilinx Answer 11630).