The read control logic for the transmit FIFO in the example design might not be able to provide a fast enough turnaround of frames at the Client transmitter interface when the core is operating in Deficit Idle Count mode.
The patch below fixes this issue with the example design FIFOs.
Install the patch as follows:
1. Extract the contents of the ".zip", ".gtar.gz", or "tar.gz" archive to the root directory of the Xilinx installation. Select the option that allows the extractor to overwrite all of the existing files and maintain the directory structure pre-defined in the archive.
Determine the Xilinx installation directory by entering the following at the command prompt:
UNIX or Linux
Determine the Xilinx installation directory by typing the following:
NOTE: You might need to have system administrator privileges to install the patch.
2. After installing the patch, regenerate the LogiCORE 10 Gigabit Ethernet MAC v7.0 Core in CORE Generator. The core and supporting files produced will contain the fix mentioned above.
The FIFOs have been completely re-written and after generating the Core the below files in the example design:
will be replaced with:
The old FIFO hierarchy for the FIFOs was:
Client_loopback - xgmac_fifo - receive_fifo - local_link_fifo - data_control_fifo
Client_loopback - xgmac_fifo - transmit_fifo - local_link_fifo - data_control_fifo
The new hierarchy for the FIFOs is:
Client_loopback - xgmac_fifo - rx_fifo - fifo_ram
Client_loopback - xgmac_fifo - tx_fifo - fifo_ram