Why does the output of my FROM and TO registers appear to be incorrect when I use the Free Running Clock with Hardware in the Loop (HITL) Co-Simulation?
This is because the model running in hardware (also known as the hardware design) is not synchronous to Simulink, and there might be several thousand hardware clock cycles between the time Simulink writes register 1 and register 2 through the Hardware in the Loop interface.
This might not be a problem for a design where you are just setting a flag and do not care how many clock cycles happen between events.
If this is a concern, there are two possible solutions:
1. In the case where your control needs to be synchronized with the data, the recommended solution would be to concatenate your control signals with your data and then use a slice block to separate them in the hardware design.
-- Since data is written in 32-bit words to the hardware design, if your concatenated bit widths become larger than 32 bits, solution 2 is the recommended flow.
2. In a case where your control signals need to be synchronized with each other, but not with the data, you could also concatenate all your control signals together and feed them into a FIFO, then read them out of the FIFO in the hardware design.
See (Xilinx Answer 24288) for more information on using the Shared Memories.
See (Xilinx Answer 24290) for information on when Shared Memories are supported.