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AR# 23208

8.2i NetGen, Timing Simulation - Known Issues with NetGen

Description

Keywords: simulate, TRACE, TRCE, anno, mismatch, problems

This Answer Record contains Known Issues for NetGen 8.2i.

Solution

Q1. NetGen takes a lot longer to run and uses more memory compared to older versions.
A1. See (Xilinx Answer 21749).

Q2. Delay from pad S to pin S of X_SFF is not matching between TRACE and SDF for Spartan-3E.
A2. This issue is fixed in 8.2 Sp2.

Q3. Tgck is not matching between TRACE and SDF for X_FF for Spartan-3E.
A3. This issue is fixed in 8.2 Sp2.

Q4. Setup is not adjusted for IOB X_SFF for Spartan-3E.
A4. This issue is fixed in 9.1.

Q5. Setup delay of R wrt CLK for the X_SFF is not matching between TRACE and SDF for Virtex-4.
A5. This issue is being investigated by Xilinx.

Q6. RAM32X1S to RAM32X1S path between TRACE and SDF are not matching for Virtex-4.
A6. This issue is being investigated by Xilinx.

Q7. TRACE and SDF delays are not matching for clock network delays for Virtex-II Pro.
A7. This issue is being investigated by Xilinx.

Q8. Setup is not adjusted correctly for X_FDDRRSE for Spartan-3E.
A8. This issue is being investigated by Xilinx.

Q9. RAM16X1S test case setup adjusted is not correct for Virtex-4.
A9. This issue is being investigated by Xilinx.

Q10. GT setup adjustment is off by 100 ps for Virtex-II Pro.
A10. This issue is being investigated by Xilinx.

Q11. Delay annotated on X_IDELAY does not match with Tidid for Virtex-4.
A11. This issue is being investigated by Xilinx.

Q12. Why do I receive false setup and hold checks in the ISERDES when my IOBDELAY_VALUE is non-zero?
A12. See (Xilinx Answer 22526)

Q13.NetGen does not tie the GSR correctly when using a STARTUP block.
A13.This issue is being investigated by Xilinx.
AR# 23208
Date Created 09/04/2007
Last Updated 03/27/2009
Status Archive
Type General Article