| AR# | 23235 |
| Part | IP-Processor |
| Last Modified | 2006-04-11 00:00:00.0 |
| Status | Active |
| Keywords | OPB_PCI, opb_timeout, Processor IP |
Keywords: OPB_PCI, opb_timeout, Processor IP
The opb_pci_v1_02_a bridge incorrectly asserts opb_timout on the next read address submitted to the bridge after a Master Abort transaction has occurred. The test bench performs an OPB to PCI burst read where the first address at offset 0x00 is set up so that the PCI Target does not respond, which forces a Master Abort condition.