8.1i EDK Sp2 - wrpfifo_v2_00_a, Write Packet FIFO returns an Error Acknowledge when a PLB Master writes to its reset port

Description

Keywords: Processor IP, wrpfifo_v2_00_a, packet FIFO

In the Write and Read Packet FIFO V2_00_a, the FIFO's bus interface returns an Error Acknowledge when a PLB Master writes to the Soft Reset register address (of the FIFO register space). This Error Acknowledge causes a PLB bus error and ultimately a Machine Check interrupt to the PPC405.

Solution