Solution

For System Generator for DSP release notes from other release versions, see (Xilinx Answer 29595).

Known Issues in System Generator for DSP 8.1.01

System Generator for DSP 8.1.01 is a minor update, and is highly recommended for all System Generator for DSP 8.1 users. Please read the documentation as it answers questions you might have about changes to the functionality or the look from previous versions of System Generator for DSP. The System Generator User Guide PDF Version is accessible from:

http://www.xilinx.com/products/design_resources/dsp_central/grouping/index.htm


Support Software Issues

1. What software do I need to install System Generator for DSP? See (Xilinx Answer 17966).

2. XST bus elaboration might cause interface changes. See (Xilinx Answer 18650).

3. Why is my old System Generator for DSP missing, or seems to have disappeared when running xlVersion after installing 8.1? See (Xilinx Answer 22756).

4. NOTE: The Hardware in the Loop Ethernet Co-Simulation System ACE file has been updated. You should rerun the CF card update utility to make sure that you have the latest version installed on your System ACE Compact Flash Card.


Xilinx Blockset Issues

1. Why do I see simulation mismatches with the DDS v4.0 when both the reset port and pipelining are enabled? See (Xilinx Answer 22709).

2. PicoBlaze compiler script fails when using long module names. See (Xilinx Answer 16924).

3. Why does XST "Error 1370 ..." occur when using Verilog as my target language with a DDS v4.0 or v5.0 in my design? See (Xilinx Answer 22713).

4. Simulation mismatched for the reloadable DA FIR when performing back-annotated simulation. See (Xilinx Answer 19505).

5. Why does my System Generator for DSP 6.3 or 7.1 design (which passed generics to the black box for port widths) fail in System Generator for DSP 8.1? See Xilinx (Answer 22715).

6. Why does my design fail in hardware if I use the reset port on the FIFO block? See (Xilinx Answer 23577).

7. Why are my Gateway In blocks behaving differently between System Generator for DSP 7.1, 8.1 and 8.1.01? See (Xilinx Answer 23250).

8. Why do I see the following error "Internal Block Error: This block set an illegal type on its "gw_out_inport" port. The type setting was illegal because Unknown type"? See (Xilinx Answer 23252).

9. When using the Viterbi with an enable pin, why do I see a difference between my System Generator for DSP 7.1 design and my System Generator for DSP 8.1 design? See (Xilinx Answer 23259).

10. Why does my design fail to generate when using a FIFO block, From FIFO block, or To FIFO block in my design, and my target path is more than 160 characters? See (Xilinx Answer 23614).

11. When a shared memory "To FIFO" depth is greater than 512, an error message is reported by the EDK processor block stating, "An error was encountered when generating the memory maps, Error using ==> set_param See (Xilinx Answer 23756).

General Issues

1. The following error is reported during generation: "Undefined function or variable." See (Xilinx Answer 15190).

2. Generation fails when the Simulation Stop Function is defined for a model. See (Xilinx Answer 18623).

3. User Hardware Co-Sim files disappear when installing System Generator for DSP update. See (Xilinx Answer 18646).

4. JTAG Hardware Co-Sim with non-Xilinx parts in the chain causes error. See (Xilinx Answer 19599).

5. Why does my simulation fail if my Simulink simulation start time is not set to zero? See (Xilinx Answer 23251).

6. How can I improve the synthesis results of the clock wrapper clock enable logic? See (Xilinx Answer 23253).