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AR# 23269

NetGen - "INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM simulation primitives... "

Description

The following information messages occur while the simulation netlist is being generated in NetGen:

INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM

simulation primitives and has to be used with SIMPRIM simulation library for

correct compilation and simulation.

INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM

simulation primitives and has to be used with SIMPRIM library for correct

compilation and simulation.

What do these messages mean?

Solution

This information indicates that the simulation primitives in generated netlist are from SIMPRIM library which can be used for post-translate, post-MAP and post-PAR simulation.

This is just information letting you know that you need to have all your libraries mapped and compiled before simulation.

Please see the "CompXLib" section in the Synthesis and Simulation Guide at:

http://www.xilinx.com/support/software_manuals.htm

For more details on compiling the Xilinx libraries for simulation.

AR# 23269
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article