The following information messages occur while the simulation netlist is being generated in NetGen:
INFO:NetListWriters:633 - The generated Verilog netlist contains Xilinx SIMPRIM
simulation primitives and has to be used with SIMPRIM simulation library for
correct compilation and simulation.
INFO:NetListWriters:635 - The generated VHDL netlist contains Xilinx SIMPRIM
simulation primitives and has to be used with SIMPRIM library for correct
compilation and simulation.
What do these messages mean?
This information indicates that the simulation primitives in generated netlist are from SIMPRIM library which can be used for post-translate, post-MAP and post-PAR simulation.
This is just information letting you know that you need to have all your libraries mapped and compiled before simulation.
Please see the "CompXLib" section in the Synthesis and Simulation Guide at:
For more details on compiling the Xilinx libraries for simulation.