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AR# 23276

8.1i MAP - When using an OBUFDS with a DIFF_SSTL18_II I/O standard, the outputs are not inverted when the logic is reset


Keywords: SRVAL, complementary single ended, CSE, MAP

When I examine the implementation of a DIFF_SSTL18_II OBUFDS in the FPGA Editor, the SRVAL for both registers is set to the same value, resulting in an incorrect reset state since the P and N side are set to the same value. Why does this occur?

When using an OBUFDS with a complementary single ended I/O standard (i.e. DIFF_SSTL18_II), the registers are duplicated by MAP to create the P and N signals for the differential pair. However, when the registers are duplicated, the SRVAL is set to the same value. Consequently, when they are reset, the P and the N side are the same, which is incorrect.


You can work around this issue by manually setting the SRVAL in the FGPA Editor.

This issue was fixed in ISE 8.2i.
AR# 23276
Date Created 09/04/2007
Last Updated 05/05/2009
Status Archive
Type General Article