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AR# 23277

FPGA I/O - What is a safe time limit for an FPGA-output driving High to be shorted to Ground?


There are no I/O short circuit specifications in the Xilinx data sheets. What is a safe time limit for an FPGA-output driving High to be shorted to Ground or an FPGA-output driving Low shorted to VCC? Can the Spartan/Virtex FPGAs survive this condition?


This is clearly an undesired condition that should never be intended in any design. An I/O short circuit test or any other form of short circuit test is not a part of the typical Xilinx test suite performed on every single device. Consequently, Xilinx recommends that such a condition always be avoided.

Purely as a qualitative test of robustness, with no intention to characterize or estimate reliability of these devices, experiments have been conducted in the past where the various I/Os of the different Virtex/Spartan families have been shorted to Ground or VCC with outputs programmed for strongest drive strength. From these experiments, Xilinx FPGAs have been observed to sink or source up to 120 mA in the short circuit condition without damage. However, the correlation of these results to various lots or fab processes has not been studied. This condition has been maintained over days and weeks with no latent damage seen. The devices used in these experiments were not analyzed for possible patent defects or degradation.

AR# 23277
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article