When I analyze a VHDL design, the following error occurs:
"ERROR:Xst:2585 Port <port_name> of instance <inst_name> does not exist in definition <def_name>"
Compare the component declaration and instantiation to the submodule that is instantiated. When this error occurs, the declaration matches the instantiation, but it does not match the port declarations of the submodule.
To solve this problem, change either the port declarations in the declaration/instantiation pair or the submodule port declarations so that the two match. This error is specific to the quantity and names of the ports in the submodule.