Some logic is trimmed as unused from my design starting with a RAM component whose SPO output feeds back to the input; this causes the following error to occur:
"ERROR:MapLib:820 - LUT2 symbol "b2.rp_3_i_m2" (output signal=rp_3_i_m2(0))
has an equation that uses input pin I0, which no longer has a connected
signal. Please ensure that all the pins used in the equation for this LUT
have signals that are not trimmed (see trim report for details on which
signals were trimmed)."
Since the DPO output is used elsewhere in the design, why does this trimming occur?
MAP uses simulation to determine whether logic is used or unused in a design. In this case, a bug in the simulation code incorrectly causes the RAM to be trimmed. This issue has been fixed for ISE version 8.2i. For earlier revisions, you can work around this issue by setting the following environment variable:
setenv XIL_MAP_BOOT_CYCLE_POP_COMPLEX 1
For general information about setting ISE environment variables, see (Xilinx Answer 11630).