When I analyze a VHDL design, the following warning occurs:
"Warning:Xst:2591 <attribute_name> on <entity/component/instance> in <XCF> overrides <generic/parameter on entity/component/instance>. It is possible that simulator will not take this attribute into account"
This message is a general warning message indicating that the synthesis attribute is different from the generic or the parameter. Consequently, simulators do not take this into account and mismatches can occur. The best way to work around this issue is to avoid the synthesis attributes and only use the generics or parameters.