Main
Home  :  Support  :  Answers  :  8.1.01.p01 System Generator for DSP - Why are the DSP48 Macro Reset and Clock Enable ports swapped?

8.1.01.p01 System Generator for DSP - Why are the DSP48 Macro Reset and Clock Enable ports swapped?

AR# 23292

Search For Another Answer
Topic SW-SysGen
Last Updated 05/10/2006
Status Active
Description

Keywords: MATLAB, Simulink, CE, RST, switched, 8.1, 8.1.01, service, pack, 01, sp1

Why are the DSP48 Macro Reset and Clock Enable ports swapped?

Solution

This problem is due to a bug in the DSP48 Macro when global reset and enable are used together.

This issue has been fixed in System Generator for DSP Path 8.1.01.p01 and later. See (Xilinx Answer 23293) for more information.
 
 
/csi/footer.htm